1. Field of the Invention
The present invention relates to a television receiver; a video signal processing device, an image processing device, and an image processing method.
2. Description of the Related Art
In recent years, the methods of broadcasting television signals have been diversified. For instance, not only have NTSC (National Television System Committee) signals been broadcasted using a ground wave but also both NTSC signals and high-definition signals have been broadcasted using a broadcasting satellite (BS). Further, just recently, digital signals have been broadcasted using a communication satellite (CS).
With the diversified methods of broadcasting, television receivers are demanded to have a capability of receiving various types of signals from such diversified broadcasting methods to display corresponding images.
Each of the different broadcasting methods uses a video format which is different from one another. For example, the NTSC signal broadcasting uses a video format of 525 horizontal scanning lines/interlace scanning, while the high-definition signal broadcasting uses a video format of 1125 horizontal scanning lines/interlace scanning. Further, in recent years, television receivers have been requested to display video signals having video formats of VGA (video graphics array) and SVGA (super VGA) which are output from computes. As such, the demands on the display function of television receivers have increasingly become strong.
When a television receiver capable of displaying video signals having a variety of video formats is attempted to be realized, one may consider providing different conversion devices for input signals having different image formats. Such a configuration, however, requires the same number of conversion devices as that of the possible different image formats, thereby increasing the circuits size and the cost.
A conventional image processing device for performing digital image processing for video signals such as television signals is shown in FIG. 26. Referring to FIG. 26, the image processing device includes a digital signal processing circuit 2200 constructed to perform a predetermined image processing for video signals and at least one field memory and/or frame memory 2202.
In the case of a moving-image real-time processing, for example, a frame memory 2202A and a field memory 2202B are used for motion detection, while a frame memory 2202C is used for motion adaption interpolation. An additional frame memory (not shown) may be used for time-axis conversion for converting a high-definition signal into an NTSC signal, for example.
Thus, a conventional digital image processing circuit heads more field memories or frame memories as more types of image processing are required. This is disadvantageous in the aspects of reducing the cost and size of the device. Dynamic random access memories (DRAMs) having a capacity of 1 to 2 M bits are used for general type field memories and frame memories. These DRAMs are extremely small in memory capacity compared with presently mainstream 10M-bit and 54M-bit dynamic RAMs, but are not so different in cost and chip size from the latter.
As the number of field memories and/or frame memories increases; the number of terminal pins of the digital signal processing circuit 2200 increases propertionally, thereby increasing the size of the resultant IC package.
Another problem is that the system with the above configuration is poorly adaptive to a variety of applications. For example, a system constructed for the NTSC signal using field memories having a capacity of 1.5 M bits is not used for the high-definition signal which needs field memories having a capacity of about 4 M bits.
Moreover, the usage of each of such a number of field memories and/or frame memories in restricted or specified in accordance with functions defined by a processing section of the digital signal processing circuit 2200. Such a conventional image processing device therefore generally fails to be used for a variety of applications.
Conventionally, therefore, when one television receiver is intended to receive a variety of video signals such as an NTSC signal, a RS signal, a high-definition signal, and a signal output from a computer, it is required to incorporate all of the different types of digital signal processing circuits, together with relevant field/frame memories, exclusive for respective types of video signals. The resultant device is extremely high in cost and large in size.
In addition to the current demands being placed on the digital signal processing circuitry, with the onset of digital broadcasting and the enhancement of the broadcasting image quality, a video signal processing circuit incorporated in a television receiver and the like similarly has been demanded to have a function of processing video signals having different formats. Moreover, such a video signal processing circuit has been demanded to have a function of displaying as such information as possible simultaneously, such as a double-screen display end a multi-screen display. Under these circumstances, a single-instruction multiple-data (SIMD) type video signal processor has been used as the video signal processing circuit.
The SIMD video signal processor processes a video signal for each horizontal scanning line, and includes N processor elements PE1 to PEN wherein N is an integer more than the number of effective phials connected to one horizontal scanning line. Each of the N processor elements PE1 to PEN processes video data corresponding to one of the pixels connected to one horizontal scanning line.
FIG. 32 illustrates a configuration of a conventional video signal processor 3100. The video signal processor 3100 includes a data input register 3101, an operator 3102, and a data output register 3105.
The data input register 301 outputs a plurality of serially input video data units to the operator 3102 in parallel. The data input register 3101 has a width of a bits and a depth of N words. The bit width a of the data input register 3101 is larger than a bit width of a general video signal to be processed. This is because there arises instances where a current luminance signal and a luminance signal delayed by one field must be input into the data input register 3101 simultaneously, for example.
The operator 3102 performs a predetermined arithmetic operation for the plurality of video data units output from the data input register 3101 in parallel. The operator 3102 includes N processor elements PE1 to PEN. Each of the processor elements PE1 to PEN includes a small-capacity memory 3103 which holds the input data and operation results and an operating element 3104 which performs a predetermined signal processing operation.
The data output register 3105 outputs the plurality of video data units processed by the operator 3102 in series. The data output register 3105 has a width of t bits and a depth of N words. The bit width t of the data output register 3108 is also larger than a bit width of a general video signal to be processed. This is because there arises instances where an output video signal and data relating to a motion delayed by one field must be output from the data output register 3105 simultaneously, for example.
Hereinbelow, the operation of the video signal processor 3100 will be described, taking as an example a process of removing a horizontal high frequency band component included in a video signal, i.e., a processing of performing horizontal low-pass filtering for a video signal (hereinbelow, referred to as an LPF processing).
FIG. 33 illustrates operations of the data input register 3101, the operator 3102, and the data output register 3105 in the LPF processing. In FIG. 33, the x-axis represents the time.
The video signal processor 3100 operates in accordance with a horizontal synchronous signal which defines horizontal blanking periods and effective video periods as shown in FIG. 33.
During an effective video period Pi, a plurality of video data units corresponding to a plurality of effective images connected to one horizontal scanning lines are input into the data input register 3101 in series. For example, one horizontal scanning line may be the i-th horizontal scanning line. Hereinbelow, the i-th horizontal scanning line is referred to as the i line wherein i is an arbitrary integer.
During a horizontal blanking period Bi following the effective video period Pi, the plurality of video data units corresponding to the i line input into the data input register 3101 are transferred to the operator 3102 in parallel.
During an effective video period Fi+1 following the horizontal blanking period Bi, the LPF processing is performed for the plurality of video data units corresponding the i line.
During a horizontal blanking period Bi+1 following the effective video period Pi+1, a plurality of LPF-processed video data units corresponding to the i line are transferred to the data output register 3105 in parallel.
During an effective video period Pi+2 (not shown in FIG. 33) following the horizontal blanking period Bi+1, the plurality of LPF-processed video data units corresponding the i line are output from the data output register 3105 in series.
The above-descried process is also performed for a plurality of video data units corresponding to an (Ixe2x88x921) line and a plurality of video data units corresponding to an (i+1) line.
FIG. 34 diagrammatically illustrates the LPF processing performed by the operator 3102. In FIG. 34, the operator 3102 is shown to performs the LPF processing for video data units Dj-2, Dj-1, Dj, Dj+1, Dj+2 corresponding to the i line, and output LPF-processed video data units Dxe2x80x2j-2, Dxe2x80x2j-1, Dxe2x80x2j, Dxe2x80x2j+1, Dxe2x80x2j+2 corresponding to one i line.
The LPF-processed video data unit Dxe2x80x2j is obtained by the calculation of expression (1) below:
Dxe2x80x2j=xc2xcxc2x7Dj-1+xc2xdxcx9cDj+xc2xcxcx9cDj+ixe2x80x83xe2x80x83(1)
The calculation of expression (1) is performed by the processor element PEj. Similar calculations to that of expression (1) are performed by the processor elements PDj-2, PEj-1, PEj+1, PEj+2. Only one LPF processing is performed by each of the processor elements PEj-2, PEj-1, PEj, PEj+1, PEj+1 for one line. In this way, the LPF-processed video data units Dxe2x80x2j-2, Dxe2x80x2j-1, Dxe2x80x2j, Dxe2x80x2j+1, Dxe2x80x2j-30 2 corresponding to the i line are obtained.
Thus, as described above, a plurality of video data units corresponding to one horizontal scanning line can be processed using a video signal processor including the number of processor elements equal to or more than the number of effective pixels connected to one horizontal scanning line.
In order to make video apparatuses such as television receivers more prevailing, further cost reduction of the video signal processor, as well as the sophistication thereof, are essential.
In the above-described conventional video signal processor, however, if the number of processor elements included in the video signal processor is smaller than the number of effective pixels connected to one horizontal scanning line, video data units corresponding to the effective pixels which have no corresponding processor elements fail to be processed. To avoid this problem, the number of processor elements included in the video signal processor must be increased as the number of effective pixels connected to one horizontal scanning line increases. This causes an increase in the cost of the video signal processor when the processing of high-precision video signals is involved.
An object of the present invention is to provide a television receiver and a video signal processing device which are adaptive to a variety of broadcasting methods without increasing the circuit size and the cost.
Another object of the present invention is to provide image processing device/method with a small-size circuit configuration which can be used for a variety of applications.
Still another object of the present invention is to provide image processing device/method which effectively utilize resources inside the device to perform efficient high-level image processing.
Still another object of the present invention is to provide an video signal processing device with a reduced cost.
The television receiver including a display device capable of displaying a video signal having a predetermined display format of this invention includes: a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.
In one embodiment of the invention, each of the plurality of video signal sources includes at least one of a NTSC decoder, a MUSE decoder, and a digital decoder.
Alternatively, the television receiver including a display device capable of displaying a video signal having a predetermined display format of this invention includes; a plurality of video signal sources; a selection circuit for selecting at least two of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of each of the at least two video signals selected by the selection circuit into a predetermined display format, and processing the at least two video signals so that synthesized images are displayed on the display device, wherein a video signal output from the processor is supplied to the display device.
In one embodiment of the invention, each of the plurality of video signal sources includes at least one of an NTSC decoder, a MUSE decoder, and a digital decoder.
According to another aspect of the invention, a video signal processing apparatus is provided. The video signal processing apparatus includes: a plurality of video signal input terminals for receiving a plurality of video signals; a selection circuit for selecting one of the plurality of video signals input via the plurality of video signal input terminals; and an image processor for converting a format of the video signal selected by the selection circuit into a predetermined display format.
Alternatively, the video signal processing apparatus of this invention includes: a plurality of video signal input terminals for receiving a plurality of video signals; a selection circuit for selecting at least two of the plurality of video signals input via the plurality of video signal input terminals; and an image processor for converting a format of each of the at least two video signals selected by the selection circuit into a predetermined display format, and synthesizing the at least two video signals.
According to still another aspect of the invention, an image processing device is provided. The image processing device includes: an input section for receiving image data to be processed; a digital signal processing section including a plurality of processing elements allocated to respective pixels corresponding to one scanning line in a one-to-one relationship for performing a same operation in accordance with a common instruction, the digital signal processing section receiving, processing, and outputting the image data for each scanning line; an image memory having a fixed memory region and capable of performing a write operation and a read operation in parallel and independently, the image memory receiving and outputting the image data for each scanning line; an output section for outputting processed image data; data bus means for connecting the input section, the digital signal processing section, the image memory, and the output section with one another; and control means for controlling the input section, the digital signal processing section, the image memory, and the output section in accordance with program data.
In one embodiment of the invention, the digital signal processing section includes; a data input portion for receiving in parallel for each scanning line at least one image data unit corresponding to at least one respective video signal; and a data output portion for outputting in parallel for each scanning line the at least one image data unit processed for each scanning line by the plurality of processing elements, wherein a data input operation for each scanning line by the data input portion, a processing operation for each scanning line by the plurality of processing elements, and a data output operation for each scanning line by the date output section are performed in a pipeline manner.
In another embodiment of the invention, the image memory includes: data write means for sequentially writing the input image data into the memory region in sequential addresses; data read means for reading the images data to be output from the memory region in sequential addresses; and pointer control means for controlling a write pointer and a read pointer for indicating a write address and a read address in the memory region, respectively, in accordance with the program data.
In still another embodiment of the invention, the image memory further includes: a plurality of input buffers each having at least first and second input buffer portions with a respective predetermined memory capacity; and means for controlling the plurality of input buffers such that when the first input buffer portion of the input buffer is filled with image data, writing of input image data into the second input buffer portion is started, and image data is read from the first input buffer portion to be written into the memory region, and when the second input buffer portion is filled with image data, writing of input image data into the first input buffer portion is started, and image data is read from the second input buffer portion to be written into the memory region.
In still another embodiment of the invention, a data rate at which image data is written into the memory region from the input buffer is selected to be different from a data rate at which image data is written into the input buffer.
In still another embodiment of the invention, the image memory further includes: a plurality of output buffers each having at least first and second output buffer portions with a respective predetermined memory capacity; and means for controlling the plurality o output buffers such that when the first output buffer portion of the output buffer has no image data, reading of image data from the second output buffer portion is started, and image data read from the memory region is written into the first output buffer portion, and when the second output buffer portion has no image data, reading of image data from the first output buffer portion is started, and image data read from the memory region is written into the second output buffer portion.
In still another embodiment of the invention, a data rate at which image data is written into the output buffer from the memory region is selected to be different from a data rate at which image data is read from the output buffer.
In still another embodiment of the invention, the data bus means includes; a first data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the digital signal processing section; a second data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the image memory; a third data bus portion for electrically connecting a data output terminal of the digital signal processing section with a data input terminal of the image memory; a fourth data bus portion for electrically connecting a data output terminal of the image memory with a data input terminal of the digital signal processing section; a fifth data bus portion for electrically connecting a data output terminal of the input section with a data input terminal of the output section; a sixth data bus portion for electrically connecting a data output terminal of the digital signal processing section with a data input terminal of the output section; and a seventh data bus portion for electrically connecting a data output terminal of the image memory with a data input terminal of the output section.
It still another embodiment of the invention, all of the first to seventh data bus portions are formed on a semiconductor chip.
In still another embodiment of the invention, the control means includes; program data holding means for holding program data defining operation modes for the input section, the digital signal processing section, the image memory, the output section, and the data bus means; and program data distribution means for receiving program data and distributing the program data into the program data holding means.
According to still another aspect of the invention, an image processing method for processing image data by the image processing device is provided. The method includes the steps of: receiving image data corresponding to one video signal by the input section; performing a first processing for the image data output from the input section to the digital signal processing section by the digital signal processing section; writing the image data output from the digital signal processing section after the first processing into the image memory to temporarily store the image data in the image memory; and receiving the image data read from the image memory by the digital signal processing section again to perform a second processing.
In one embodiment of the invention, the image processing method further includes the steps of: writing the image data output from the digital signal processing section after the second processing into the image memory to temporarily store the image data into the image memory; and receiving the image data read from the image memory by the digital signal processing section again to perform a third processing.
Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving image data corresponding to one video signal by the input section; writing the image data output from the input section into the image memory to temporarily store the image data in the image memory; supplying the image data from the input section and the image data read from the image memory to the digital signal processing section in parallel, and performing a predetermined processing between these image data.
In one embodiment of the invention, the image data is read from two output ports of the image memory by delaying the image data by a predetermined delay amount and input in parallel into the digital signal processing section, and the predetermined processing is performed between the two units of image data from the image memory and the image data from the input section.
Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: writing only a portion of the image data corresponding to a portion of pixels for each scanning line and/or a portion of scanning lines for each field among the image data corresponding to one video signal into the image memory to temporarily store the portion of the image data in the image memory; and reading from the image memory the image data in the order in which the pixels and scanning lines have been written to the image memory.
Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: writing image data corresponding to one video signal into the image memory to temporarily store the image data in the image memory; reading the image data from the image memory intermittently for each pixel or for each scanning line; and supplying the image data read from the image memory to the digital signal processing section, and interpolating image data at positions of pixels or scanning lines which had been skipped in the intermittent reading of the image memory.
Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving first and second image data units corresponding to two image signals which are asynchronous from each other by the input section; writing the first image data unit output from the input section into the image memory to temporarily store the first image data in the image memory; supplying the second image data unit output from the input section to the digital signal processing section, and simultaneously reading the first image data unit from the image memory to supply to the digital signal processing section in synchronization with the supply of the second image data unit; and performing a predetermined processing for the first and second image data units input in synchronization with each other by the digital signal processing section.
Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving first and section image data units corresponding to two image signals which are asynchronous from each other by the input section; supplying the first image data unit output from the input section to the digital signal processing section to perform a predetermined processing; supplying the first image data unit output from the digital signal processing section to the image memory, and simultaneously supplying the second image data unit output from the input section to the image memory; and reading the first and second image data units from the image memory in synchronization with a synchronous signal other than synchronous signals relating to the first and second image data units.
Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving image data corresponding to one video signal by the input section; supplying a former half of the image data output from the input section to the digital signal processing section during a first period; writing the image data output from the input section into the image memory and reading the written image data after a predetermined delay time; and supplying a letter half of the image data output from the image memory to the digital signal processing section during a second period.
In one embodiment of the invention, the image processing method further includes the steps of: writing the former half of the image data output from the digital signal processing section into the image memory and reading the written image data after a predetermined delay time; outputting the former half of the image data read from the image memory from the output section; outputting the letter half of the image data from the digital signal processing section; and outputting the latter half of the image data output from the digital signal processing section from the output section in succession with the former half of the image data.
In another embodiment of the invention, the image processing method further includes the steps of: adding a first overlap portion which overlaps a head portion of the latter half of the image data by a predetermined number of pixels to a tail portion of the former half of the image data input into the digital signal processing section during the first period; adding a second overlap portion which overlaps a tail portion of the former half of the image data by a predetermined number of pixels to a head portion of the latter half of the image data input into the digital signal processing section during the second period; and removing the first and second overlap portions at a stage of outputting the image data outside from the output section.
Alternatively, the image processing method for processing image data by the image processing device of this invention includes the steps of: receiving image data corresponding to one video signal by the input section and performing a low-pass filtering processing by the input section; and supplying the image data output from the input section to the digital signal processing section or the image memory, and performing a decimation processing for information compression of the image data.
According to still another respect of the invention, a video signal processing device is provided. The video signal processing device includes: a first converter for receiving a plurality of video data units corresponding to a plurality of pixels connected to one scanning line as an input video signal, and converting the plurality of video data units into a plurality of video data sets, each of the plurality of video data sets including at least two video data units; an operator for processing the plurality of video data sets and outputting a plurality of processed video data sets; and a second converter for converting the plurality of processed video data sets into a plurality of processed video data units corresponding to a plurality of pixels connected to one scanning line, and outputting the plurality of processed video data units as an output video signal.
In one embodiment of the invention, the operator includes a plurality of processor elements, and each of the plurality of processor elements processes at least two image data units included in each of the plurality of video data sets.
Thus, the invention described herein makes possible the advantages of (1) providing a television receiver and a video signal processing device which are adaptive to a variety of broadcasting methods, without increasing the circuit size and the cost, (2) providing image processing device/method with a small-size circuit configuration which can be used for a variety of applications, (3) providing image processing device/method which effectively utilize resources inside the device to parform efficient high-level image processing, and (4) providing an video signal processing device with a reduced cost.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.